The present invention relates to a nonvolatile semiconductor memory device and a manufacturing technique thereof. More particularly, the present invention relates to a technique effectively applied to a nonvolatile semiconductor memory device embedded on the same substrate along with a semiconductor device having a logic operating function, for example, a microcomputer.
By embedding a semiconductor nonvolatile memory cell on the same silicon substrate along with a logic semiconductor device, a high-performance semiconductor device can be formed. Such a semiconductor device is widely used as an embedded microcomputer in industrial equipment, household appliances, and in-vehicle equipment, etc. Usually, the nonvolatile memory embedded on the same substrate along with the microcomputer stores the program required by the microcomputer, and the program is read and used as occasion demands. As a cell structure of the nonvolatile memory suitable to be embedded along with the logic semiconductor device, a split gate type memory cell composed of a select MOS transistor and a memory MOS transistor can be used. Since adoption of this structure makes it possible to reduce the area of a peripheral circuit for controlling the memory, it is primarily used. The relating technical documents are, for example, Japanese Patent Laid-Open No. 5-048113 (hereinafter “Patent Document 1”); Japanese Patent Laid-Open No. 5-121700 (“Patent Document 2”); IEEE, VLSI Technology Symposium, 1994 proceedings, pp. 71-72 (“Non-patent Document 1”); and IEEE, VLSI Technology Symposium, 1997 proceedings, pp. 63-64 (“Non-patent Document 2”).
As a charge storing structure of the memory MOS transistor, a floating gate structure in which charges are stored in an electrically isolated conductive polysilicon (Patent Document 2 and Non-patent Document 1) and a MONOS structure in which charges are stored in an insulator such as a silicon nitride film that has a characteristic to store the charges (Patent Document 1 and Non-patent Document 2) are available. The floating gate structure is widely used in a code storage flash memory for a mobile phone and a data storage large-capacity flash memory and has good charge storing characteristic. However, it becomes more and more difficult to acquire a coupling ratio required for potential control of the floating gate due to the further scaling down, and its structure becomes complicated. In order to prevent the leakage of the retained charge, a thickness of about 8 nm or more is required for an oxide film surrounding the floating gate, and therefore scaling down for the purpose of higher speed operation and higher integration are reaching its limit. Since the charges are stored in the conductor, they are largely influenced by the defect of the oxide film to be a leakage path and the charge storing time is extremely reduced in the memory cell having the defect of the oxide film. Meanwhile, the MONOS structure is usually inferior to the floating gate structure in the charge storing characteristic, and the threshold voltage has a tendency to be decreased with a logarithm of time. Therefore, the MONOS structure is used only in the limited products though it has been known from a long time ago. However, since the charges are stored in the insulator, the MONOS structure is not so much influenced by the defect of the oxide film and can use the thin oxide film with a thickness of 8 nm or less. Therefore, it is suitable for the further reduction in size. Also, since the charge storing time is not extremely decreased due to the defect in the MONOS structure, its reliability can be easily expected, and since the memory cell structure is simple, it can be easily embedded along with the logic circuit. For these reasons, with the advance of the reduction in size, the MONOS structure has recently been drawn attention to again.
As the split gate structure particularly suitable for the reduction in size, the structure in which one of the MOS transistors is formed of a sidewall using a self-aligned manner is available (Patent Document 1 and Non-patent Document 2). In this case, an alignment margin of photolithography is unnecessary, and gate length of the transistor formed by the self-aligned manner can be made equal to or smaller than the minimum resolution dimension. Therefore, it is possible to form the finer memory cell in comparison to the conventional structure in which each of the two transistors is formed by using a photomask.
Among the split gate memory cells using the self-aligned manner, the cell, as disclosed in Non-patent Document 2, in which the self-aligned gate is formed by using the MONOS structure, is suitable to be mounted along with the high-speed logic circuit. Since the select gate side is first formed because of a structural reason, the select gate and the gate oxide film of the logic circuit portion simultaneously formed can be formed with the interface of the silicon substrate being in good condition. Since the transistor with a thin film gate for the high-speed operation that is sensitive to the interface quality can be formed, the performance of the logic circuit fabricated together and the select gate is improved.